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| Ordering number:ENN2648 CMOS IC LC66PG5XX EPROM-Mountable Type 4-bit Microcomputer Evaluation Chip for The LC665XX Series Microcomputers Overview The LC66PG5XX is an EPROM-mountable type 4-bit microcomputer for developing and evaluating programs written for the CMOS 4-bit single-chip LC665XX series microcomputers. Either 2764 or 27128 type EPROM can be mounted on the LC66PG5XX. The LC66PG5XX with the EPROM mounted can carry out the same functions as those of the LC665XX series microcomputers. Therefore, you can evaluate programs developed for application products controlled by the LC665XX series microcomputers by incorporating the LC66PG5XX into the applications before the programs are masked in the ROMs. Pin assignment Features * Either 2764 or 27128 type EPROM can be mounted. * Shrink type 64-pin configuration compatible with the LC665XX series microcomputers. Note that pull-up resistors need to be externally added. * Options provided for selecting functions. Options allowing the user to select output signal level for ports 0, 1 and 8 at the initial reset or to specify whether the watchdog timer function is employed by setting external pin levels * Instruction cycle time 0.92 to 10 microseconds. * +5V single power source. The LC66PG5XX has the 28-pin soket and 14-pin soket on the top face of the package. It also has the shrink type 64-pin terminals on the bottom face of the package. The 28-pin soket is used for mounting the EPROM containing the programs and 14-pin soket for selecting functions by options (input/output options not included). The shrink type 64-pin terminals are compatible with the LC665XX series microcomputers. Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges,or other parameters) listed in products specifications of any and all SANYO products described or contained herein. SANYO Electric Co.,Ltd. Semiconductor Company TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN N3001TN (KT)/7317KI, TS No.2648-1/14 LC66PG5XX Configurations of the LC665XX series microcomputers Model name ROM capacity RAM capacity Package Remarks LC66506A 6KB 512x 4 DIP64S FLP64 Available LC66508A 8KB 512x 4 LC66512A 12KB 512x 4 LC66516A 16KB 512x 4 LC66PG5XX 16K bytes. Externally added 512x 4 DIC64S Piggyback LC66599 16K bytes. Externally added 512x 4 PGA120 EVA chip Notes on use The LC66PG5XX is a product for developing and evaluating programs for the LC665XX series microcomputers. Keep always in mind the following considerations when using the LC66PG5XX. 1. The operating conditions are different from those of the production mask ROM . It is not recommended that the LC66PG5XX is used under the environmental conditions including high temperature and terrible humidity. 2. The electric characteristics are not the same as those of the production mask ROM. To evaluate strictly the electric characteristics at the interface with external circuits, use the recommended electric characteristics values of the production mask ROM. 3.The discrepancy in internal circuit pattern configuration between the LC66PG5XX and the production mask ROM results in the following differences between them. *Differrent initial values are set in RAMs at power ON. *Differrent noise figures (NF) are recorded. That is, the static noise intensity of the LC66PG5XX is different from that of the production mask ROM. Keep it always in mind. External dimension No.2648-2/14 LC66PG5XX Overview of terminal function Terminal name P00 P01 P02 P03 Input/ output I/O Function Input/output port P00 to P03 *Data input and output in 4-bit units or in 1bit units. *P00 to P03 used for controlling HALT mode. LC66PG5XX output format *Nch OD output Option (production chip) *Pull-up MOS or Nch OD (open drain) output *Output level at initial reset At initial reset H or L (optional) P10 P11 P12 P13 P20/SI0 P21/SO0 P22/SCK0 P23/INT0 I/O Input/output port P10 to P13 *Data input and output in 4-bit units or in 1bit units. *Nch OD output *Pull-up MOS or Nch OD output *Output level at initial reset H or L (optional) I/O Input/output port P20 to P23 *Data input and output in 4-bit units or in 1bit units. *P20 also used as SI0 terminal for serial input. *P21 also used as SO0 for serial output. *P22 also used as SCK0 for serial clock signal input/output. *P23 also used as INT0 terminal for INT0 interrupt request input . In addition, it is used for timer 0 event count input and pulse width measurement input. *Nch OD output *CMOS or Nch OD output H P30/INT1 P31/POUT0 P32/POUT1 I/O Input/output port P30 to P32 *Data input and output in 3-bit units or in 1bit units. *P30 also used as INT1 terminal for INT1 interrupt request signal. *P31 also used for burst pulse signal output from timer 0. *P32 also used for burst pulse signal output from timer 1 and PWM signal output. *Nch OD output *CMOS or Nch OD output H P33/HOLD I HOLD mode control input. *When HOLD=L, HOLD mode to be set by the HOLD instruction. *During HOLD mode "ON", restart up to the CPU by applying "H"-level signal to the HOLD terminal. *Also used as input port P33 if used together with port P30 to P32. *CPU not to be reset even if "L"-level signal is applied to the RES terminal with the P33/HOLD set to "L". The output level of the P33/HOLD terminal at power ON must not be set "L"on your application products. - - - P40 P41 P42 P43 I/O Input/output port P40 to P43 *Data input and output in 4-bit units and 1-bit units. *Also used for data input/output in 8-bit units if jointly used with port P50 to P53. *Used for ROM data output in 8-bit units if jointly used with port P50 to P53. *Nch OD output *Pull-up MOS or Nch OD output H Continued on next page No.2648-3/14 LC66PG5XX Continued from preceding page Terminal name P50 P51 P52 P53 Input/ output I/O Function LC66PG5XX output format *Nch OD output Option (production chip) *Pull-up MOS or Nch OD output At initial reset H Input/output port P50 to P53 *Data input/output in 4-bit units and 1-bit unit. *Used for input/output in 8-bit units if jointly used with port P40 to P43. *Used for ROM data output in 8-bit units if jointly used with port P40 to P43. P60/SI1 P61/SO1 P62/SCK1 P63/PIN1 I/O Input/output port P60 to P63 *Data input/output in 4-bit units and 1-bit units. *P60 terminal also used as terminal SI1 for serial input. *P61 terminal also used as terminal SO1 for serial output. *P62 terminal also used as terminal SCK1 for serial clock signal input/output. *P63 terminal also used for event count input to timer 1. *Nch OD output *CMOS or Nch OD output H P70 P71 P72 P73 O Output port P70 to P73 *Data output in 4-bit units and in 1-bit units. *The contents of output latch circuit to be input with input-related instructions. *Nch OD output *Pull-up MOS or Nch OD output H P80 P81 P82 P83 O Output port P80 to P83 *Data output in 4-bit units and in 1-bit units. *The contents of output latch circuit to be input with input-related instructions. *Pch OD output option available. *Pch OD output *CMOS or Pch OD output *Output level at the initial reset H or L (optional) P90/INT2 P91/INT3 P92/INT4 P93/INT5 I/O Input/output port P90 to P93 *Data input and output in 4-bit units and in 1bit units. *P90 also used as the INT2 terminal for INT2 interrupt request input. *P91 also used as the INT3 terminal for INT3 interrupt request input. *P92 also used as the INT4 terminal for INT4 interrupt request input. *P93 also used as the INT5 terminal for INT5 interrupt request input. *Nch OD output *CMOS or Nch OD output H PA0 PA1 PA2 PA3 O Output port PA0 to PA3 *Data output in 4-bit units and in 1-bit units. *The contents of output latch circuit to be input with input-related instructions. *Nch OD output *Pull-up MOS or Nch OD output H PB0 PB1 PB2 PB3 O Output port PB0 to PB3 *Data output output in 4-bit units and in 1-bit units. *The contents of output latch circuit to be input with input-related instructions. *Nch OD output *Pull-up MOS or Nch OD output H Continued on next page No.2648-4/14 LC66PG5XX Continued from preceding page Terminal name PC0 PC1 PC2/VREF0 PC3/VREF1 Input/ output I/O Function LC66PG5XX output format *Nch OD output Option (production chip) *CMOS or Nch OD output At initial reset H Input/output port PC0 to PC3 *Data input and output in 4-bit units and in 1-bit units. *PC2 also used as the VREF0 terminal for reference voltage input. *PC3 also used as the VREF1 terminal for reference voltage input. PD0/CMP0 PD1/CMP1 PD2/CMP2 PD3/CMP3 I Input port PD0 to PD3 *Can be selected as comparator input terminals on programs. PD0 : reference voltage input (VREF0). PD1 to PD3 : reference voltage input (VREF1) *PD0, PD1 (PD2 to PD3) selectable as comparator input ports on programs in this unit. - - Normal input PE0/TRA PE1/TRB I Input port *Selectable as three-state input port on programs. - - Normal input OSC1 OSC2 I O Terminals for system clock oscillator externally added. *Leave OSC2 open and close OSC1 for external clock signal input when external clock mode is selected. - *Ceramic resonator oscillation, RC (resistor and capacitor) or external clock selection. - RES I Terminal for system reset signal input. *CPU to be initialized when P33/HOLD="H" plus "L" level voltage is applied to the RES terminal. - - - TEST I Terminal for CPU test signal input. *Always connected to VSS during operation. - - - VDD VSS - Power source terminal - - - No.2648-5/14 LC66PG5XX LC66PG5XX special terminals Terminal name Input/ output Output type Function P0HL P1HL P8HL RAMC0 RAMC1 WDC I - Terminals for signal input to select output level at ports 0, 1 and 8 at the reset. "H" level output to be selected if "H" level signal is input to the terminals. I - Terminal for signal input to control RAM capacity. I - Terminal for signal input to contorol whether the watchdog timer function is used. The watchdog timer function to be selected if "H" level signal is input. CP1 O Pu MOS output Terminal for signal output to select clock signal edge for output latch of extended ports. IM0 to IM7 I - Terminals for instruction input from external circuits. PM0 to PM13 O O Pu MOS output Terminals for PC output to external circuits. CE Pu MOS output Terminal for signal output to contorol the CE terminal of memory externally added. Remarks : Pu MOS output ................. Pull-up MOS transistor output. CMOS output .................... Complementary MOS output. OD output .......................... Open drain output. How to mount and use EPROM on the LC66PG5XX You write assembled program data into an EPROM and mount it on the LC66PG5XX. To write data into the EPROM, you can use the EPROM writer function of the EVA-800. No.2648-6/14 LC66PG5XX Power source for EPROM Normal current drain per EPROM is in the range of 50mA and 100mA. When power capacity of an application product is not sufficient, power can be supplied to the EPROM from external independent power source. That is, the power source which is different from that on the application system can be selected. At the factory shipment, the +5V pin and VDD pin are connected on the LC66PG5XX. Therefore, power is supplied to the EPROM from the LC66PG5XX power source terminal (pin64). Of the power source pads on the package surface, +5V pad is used to supply power to the EPROM. Note The LC66PG5XX is a CMOS type IC. This reminds us that latch-up may be caused by input voltage level below the VSS level or above the VDD level. The latch-up is specific to this type of IC and destroys IC device structure or adversely affects operating functions. You should be careful about the voltage level range of the LC66PG5XX and EPROM. To start the LC66PG5XX and EPROM operation, first turn on the LC66PG5XX and then the EPROM. To stop the LC66PG5XX and EPROM operation, first turn off the EPROM and then the LC66PG5XX. Function selection by options Select the port 0, port 1 or port 8 output level at the reset, watchdog timer function and internal RAM capacity according to the options and functions of the microcomputer to be evaluated. Set as below pins 1 to 6 of the 14-pin socket on the package surface. Function type Pin No. Pin name Pin setting ON Port 0, port 1 and Port 8 output level at reset 1 2 3 P0HL P1HL P8HL OFF ON Watchdog timer 6 WDC OFF Pin setting RAM capacity RAMC1 OFF OFF ON ON RAMC0 OFF ON OFF 512W ON Stop Port output level "L" Operation Function mode Port output level "H" Internal RAM capacity 4 5 RAMC0 RAMC1 No setting for the LC665XX series microcomputers ON : +5V voltage input, OFF : Open. Pins 14, 13, 12, 11, 10 and 9 of the 14-pin socket are assigned as the +5V terminals. These terminals can be used only for supplying +5V voltage to the pins 1, 2, 3, 4, 5, and 6. Note that pin 8 is reserved for future use and should be left open. No.2648-7/14 LC66PG5XX Notes on use 1. The port output format for the LC66PG5XX is as follows : The Pch OD format is employed only for port 8. The Nch OD format is employed for the rest. Add resistors to each port according to the port output formats employed for production chips. *When optional pull-up resistors are selected for ports P0, P1, P4, P5, P7, PA and PB, add resistors of about 10k to them and connect the port to the VDD terminal. *When the optional CMOS output format is selected for port P8, add the resistor of about 1k to it and connect the port to the VSS terminal. Select the resistor in the range of 0.5k to 10k according to load balance. *When the optional CMOS output format is selected for ports P2, P3 (P33 not included), P6, P9 and PC, add the resistors of about 10 k to them and connect them to the VDD terminal. (add the resistors of more than 1 k if sink current is used.) 2. The LC66PG5XX has no feedback resistors. Add the external feedback resistor of about 1 M to the LC66PG5XX when the ceramic resonator oscillation is selected. The external capacitance is the same as that of production chips. 3. The constants and oscillation characteristics of the RC (resistor and capacitor) oscillation circuit are different from those of production chips. Set them to the oscillation frequency of production chips by making adjustments to volume resistor. 4. The operating voltage level of the LC66PG5XX must be within the range of the operating voltage of the EPROM and other ICs. That is, the level is : VDD=5Vwith 5% margin. 5. The operating environment temperature is in the range of 10C to 40C. Absolute maximum ratings at Ta = 25C, VSS = 0V Parameter Maximum voltage level Symbol VDD max VIN1 VIN2 Output voltage VOUT1 VOUT2 ION1 Output current per terminal ION2 -IOP2 ION1 Total terminal current ION2 -IDP1 Allowable power dissipation Operating temperature Storage tempurature Pd max Topr Tstg VDD P2, P3(P33/HOLD not included), P6 Other inputs P2, P3(P33/HOLD not included), P6, P7 and PA Other outputs P0, P1, P2, P3(P33/HOLD not included), P4, P5, P6, P8, P9 and PC P7, PA, PB P8 P2, P3(P33/HOLD not included), P4, P5, P6, P7 and P8 P0, P1, P9, PA, PB, PC 8 Ta=10 to 40 C DIC-64S 20 4 75 75 25 600 +10 to +40 +55 to +125 mA mA mA mA mA mW C C 3 4 3 3 4 4 mA 3 Terminal and note Condition Ratings -0.3 to +7.0 -0.3 to +15.0 -0.3 to VDD+3.0 -0.3 to +15.0 -0.3 to VDD+3.0 Unit V V V V V 1 2 1 2 Note Input voltage Note 1: Applicable only when open drain output format is selected. If the format is not selected, another standard value is used. Note 2: The self oscillation voltage level can be included in the standard value range as far as oscillation input/output is concerned. Note 3: Sink current (applicable to P8 only when CMOS output format is selected). Note 4: Source current (applicable to terminals other than P8 only when pull-up output format or CMOS output format is selected). No.2648-8/14 LC66PG5XX Recomemended operating conditions at Ta = 10C to 40C, VSS = 0V, unless otherwise specified Codnitions Parameter Operating power voltage Memory hold voltage VDDH VDD HOLD mode 1.8 6.0 V Symbol VDD VDD Terminal VDD(V) min 4.0 Ratings typ 5.0 Unit max 6.0 V Note High-level input voltage VIH1 P2, P3 (33/HOLD not included),P6 Output Nch Tr OFF 4.0 to 6.0 0.75VDD +13.5 V 1 VIH2 P33/HOLD P9, RES, OSC1 Output Nch Tr OFF 4.0 to 6.0 0.75VDD VDD V 2 VIH3 P0, P1, P4, P5, PC, PD, PE Output Nch Tr OFF 4.0 to 6.0 0.7VDD 0.8VDD 0.4VDD VDD VDD 0.6VDD V 3 VIH4 Medium-level input voltage In-phase input voltage range Low-level input voltage VIL1 VCMM VIM PE PE 3-state input format 3-state input format 4.0 to 6.0 4.0 to 6.0 V V PD, PC2, PC3 Comparator input mode 4.0 to 6.0 1.0 VDD-1.5 V P2, P3 (33/HOLD not included),P6, P9, RES, OSC1 Output Nch Tr OFF 4.0 to 6.0 VSS 0.25VDD V 2 VIL2 VIL3 P33/HOLD P0, P1, P4, P5, PC, PD, PE, TEST Output Nch Tr OFF 1.8 to 6.0 4.0 to 6.0 VSS VSS 0.25VDD 0.3VDD V V 3 VIL4 Operating frequency (instruction cycle time) fop (Tcyc) fext PE 3-state input format 4.0 to 6.0 4.0 to 6.0 VSS 0.4 (10) 0.2VDD 4.35 (0.92) 4.35 V MHz (s) MHz Externanl clock pulse input condition Frequency OSC1 See Figure 1. Input to the OSC1 terminal. OSC2 terminal left open. 4.0 to 6.0 0.4 Pulse width textH textL Same as sbove. 4.0 to 6.0 7.0 ns Fall/rise time textR textF Same as sbove. 4.0 to 6.0 30 ns Frequency fCF fCFS OSC1, OSC2 See Figure 2. See Figure 3. 4MHz 4MHz 4.0 to 6.0 4.0 to 6.0 4.0 10 MHz ms Self osillation conditions Ceramic resonator oscillation Oscillation stabilization time External RC oscillation constants Cext Rext OSC1, OSC2 See FIgure 4. 4.0 to 6.0 100 2.2 pF k Note 1: Applicable to terminals with open drain output format. VIH2 applied to P33/HOLD terminal. Note 2: Applicable to terminals with open drain output format. Note 3: VIH4, VIM and VIL4 applied when PE is used for 3-state input operation. No.2648-9/14 LC66PG5XX Electric characteristics at Ta = 10C to 40C, VSS = 0, unless otherwise specified Codnitions Parameter High-level input current Symbol IIH1 Terminal P2, P3 (33/HOLD not included),P6 IIH2 P0, P1, P4, P5, P9 PC, OSC1, RES, P33/HOLD (PD, PE, PC2 and PC3, not included) VIN =13.5V Output Nch Tr OFF VIN =VDD Output Nch Tr OFF 4.0 to 6.0 +1.0 A 1 VDD(V) 4.0 to 6.0 min Ratings typ Unit max +5.0 A 1 Note IIH3 PD, PE, PC2, PC3 VIN=VDD Output Nch Tr OFF VIN=VSS Output Nch Tr OFF 4.0 to 6.0 +1.0 A 1 Low-level input current IIL1 Input level to terminals other than PD, PE, PC2 and PC3 4.0 to 6.0 -1.0 A 2 IIL2 PC2, PC3, PD, PE VIN=VSS Output Nch Tr OFF 4.0 to 6.0 -1.0 A 2 High-level output voltage VOH1 P8 IOH= -1mA IOH= -0.1mA 4.0 to 6.0 4.0 to 6.0 4.0 to 6.0 VDD-1.0 VDD-0.5 0.4 V Low-level output voltage VOL1 P0, P1, P2, P3, P4, IOL= 1.6mA P5, P6, P9, and PC (P33/HOLD not included) V VOL2 Output off leak current IOFF1 IOFF2 IOFF3 Comparator offset voltage Hysteresis voltage VHYS VOFF P7, PA, PB P2, P3, P6, P7, PA (P2, P3, P6, P7, P8 and PA not included) P8 PD IOL= 10mA VIN=13.5V VIN=VDD VIN=VSS VIN=1.0V to VDD-1.5V 4.0 to 6.0 4.0 to 6.0 4.0 to 6.0 1.5 5.0 1.0 V A A A 6 6 4.0 to 6.0 4.0 to 6.0 -1.0 50 300 7 mV P2, P3, RES, P6, P9 and OSC1. OSC1 for external clock signal input. 4.0 to 6.0 0.1VDD V Schmidt characteristics High-level threshold voltage Low-level threshold voltage VtH 0.5VDD 0.75VDD VtL 0.25VDD 0.5VDD RC (resistor and capacitor) oscillation frequency) Cycle time Serial clock fRC OSC1, OSC2 See Figure 4. Cext=100pF5% Rext=2.2k1% 4.0 to 6.0 2.0 3.0 4.0 MHz Input Outnput tCKCY SCK0, SCK1 See the timing shown in Figure 5 and the test load in Figure 6. 4.0 to 6.0 4.0 to 6.0 4.0 to 6.0 4.0 to 6.0 4.0 to 6.0 4.0 to 6.0 0.92 2.0 0.4 1.0 3.0 0.1 s Tcyc s Tcyc s Low-level/ Input tCKL high-level/ pulse width Outnput tCKH Fall/rise time Input tCKR Outnput tCKF Continued on next page No.2648-10/14 LC66PG5XX Continued from preceding page Codnitions Parameter Data setup time Serial input Data hold time Symbol tICK tCKI Terminal SI0, SI1 See Figure 5 "Serial input/output timing" Synchronized with the rise () of the SCK0 and SCK1 signals. Output delay time Serial output tCKO SO0, SO1 See Figure 5 "Serial input/output timing" and Figure 6 "Timing load". Synchronized with the fall () of the SCK0 and SCK1 signals. INT0 high-level/ low-level/pulse width Pulse input conditions tI0H tI0L INT0 See Figure 7. *When INT0 interrupt is accepted. *When timer 0 event counter/pulse width measure input is accepted. Interrupt input to terminals other than INT0. Highlevel/low-level/ pulse width. PIN1 high-level/ low-level/pulse width RES high-level/ low-level/pulse width Comparator response speed TRS PD See Figure 8. Operating mode current drain IDDop VDD 4MHz ceramic resonator oscillation 4MHz external clock RC oscillation HALT mode current drain IDDHALT VDD 4MHz ceramic resonator oscillation 4MHz external clock RC oscillation HOLD mode current drain IDDHOLD VDD 1.8 to 6.0 2 1.2 0.01 3.5 2.5 10 A 9 4.0 to 6.0 6.5 4.0 1.0 11 8 2.5 mA 9 4.0 to 6.0 4.5 8 mA 8 4.0 to 6.0 30 s tRSH tRSL RES tPINH tPINL PIN1 *When timer 1 event counter input is accepted. *When reset signai is accepted. 3 Tcyc 2 Tcyc tI1H tI1L INT1, INT2 INT3, INT4 INT5 *When each interrupt is accepted. 2 Tcyc 4.0 to 6.0 2 Tcyc 4.0 to 6.0 0.3 s VDD(V) 4.0 to 6.0 4.0 to 6.0 min 0.3 0.3 Ratings typ Unit max s s Note Note 1: Note 2: Note 6: Note 7: Note 8: Note 9: Open drain output format and output Nch Tr OFF for input/output common ports. Open drain output format and output Nch Tr OFF for input/output common ports. Open drain output format and output Nch Tr OFF. Open drain output format and output Pch Tr OFF. Reset status. EPROM current drain not included. EPROM current drain not included. No.2648-11/14 LC66PG5XX Fig. 1 External clock input waveform (1) Capacitor externally connected type (2) Capacitor contained type Fig. 2 Ceramic resonator oscillation circuit 4MHz (Murata) C1 C2 33pF10% 33pF10% 33pF10% 33pF10% Capacitor externally connected type CSA4.00MG 4MHz (Kyocera) KBR4.0MS C2 C1 Capacitor contained type 4MHz CST4.00MG (Murata) 4MHz KBR-4.0MES (Kyocera) Fig. 3 Oscillation stable time Table1 : Recommended ceramic resonator constants Fig. 4 RC oscillation No.2648-12/14 LC66PG5XX Fig. 6 Test Loads Fig. 5 Serial input/output timing Fig. 7 INT0, INT1, INT2, INT3, INT4, INT5, PIN1, RES input timing Fig. 8 Comparator response Trs timing No.2648-13/14 LC66PG5XX Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products(including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be expor ted without obtaining the expor t license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only ; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of November, 2001. Specifications and information herein are subject to change without notice. PS No.2648-14/14 |
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